#include "system.h"

/** C O N F I G U R A T I O N   B I T S ******************************/

/*These bits specify fundamental device operation, such as the oscillator mode, 
 * watchdog timer, programming mode and code protection.
 * This does not produce executable code */

/*** Oscillator Selection bits ********
 * Internal oscillator block, port function on RA6 and RA7
 * Fail-Safe Clock Monitor disabled
 * Oscillator Switchover mode disabled
 */
#pragma config FOSC = INTIO67, FCMEN = OFF, IESO = OFF

/* Power-up Timer disabled
 * Brown-out Reset disabled in hardware and software
 * Brown Out Reset Voltage bits: VBOR set to 3.0 V nominal
 */
#pragma config PWRT = OFF, BOREN = OFF, BORV = 30

/*Watchdog Timer is controlled by SWDTEN bit of the WDTCON register
 Watchdog Timer Postscale: 1:32768
 */
#pragma config WDTEN = OFF, WDTPS = 32768                                   

/* MCLR pin enabled; RE3 input pin disabled
 * Timer1 configured for higher power operation
 * CCP2 input/output is multiplexed with RC1
 * PORTB<4:0> pins are configured as digital I/O on Reset
 */
#pragma config MCLRE = ON, LPT1OSC = OFF, PBADEN = ON, CCP2MX = PORTC

/* Stack full/underflow cause Reset
 * Single-Supply ICSP disabled
 * Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
 */
#pragma config STVREN = ON, LVP = OFF, XINST = OFF                   

/*Blocks 0,1,2,3, Boot block, and Data EEPROM are not code-protected*/
#pragma config CP0 = OFF, CP1 = OFF, CP2 = OFF, CP3 = OFF 
#pragma config CPB = OFF, CPD = OFF 

/*Block 0,1,2,3, Boot block, Configuration Register, and Data EEPROM are not write-protected */
#pragma config WRT0 = OFF, WRT1 = OFF, WRT2 = OFF, WRT3 = OFF 
#pragma config WRTB = OFF, WRTC = OFF, WRTD = OFF

/*Block 0,1,2,3, and Boot block are not protected from table reads executed in other blocks */
#pragma config EBTR0 = OFF, EBTR1 = OFF, EBTR2 = OFF, EBTR3 = OFF 
#pragma config EBTRB = OFF
